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PhD position for the FormaSig project on Formal methods in railway signalling infrastructure standardisation processes.

Research / Academic
Enschede

Description:

Fewer train delays and rail disruptions? That is the challenge in theFormaSig project, a joint research project with Eindhoven University of Technology, funded by the Dutch railroad asset manager ProRail, and the German train operator Deutsche Bahn.

The goal of the FormaSig project is to develop techniques to increase the reliability and interoperability of railroad elements, such as switches, interlockings and signalling systems. The starting points in the project are the standard interface specifications of these railroad elements, written in the SysML modelling language by the EULYNX consortium. The project aims to refine these models, making them amenable to formal verification as well as to formal, model-based testing. 

To realize a good collaboration with the industrial partners, you are expected to spend two days per week at ProRail (together with the PhD candidate from the Eindhoven University of Technology). 

Requirements:

We are looking for enthusiastic students with a MSc degree in Computer Science or Mathematics with a demonstrable interest in computer science. The candidates should have a thorough theoretical background, and an interest in the verification of complex, industrial systems.

Further, the candidate should be able to speak Dutch, or be willing to acquire the language fast.

Your application should consist of:
  • a cover letter (explaining your specific interest and qualifications);
  • a full Curriculum Vitae;
  • a list of all courses + marks and a short description of your MSc thesis;
  • references (contact information) of two scientific staff members.

INFORMATION AND APPLICATION


Deadline: May 1, 2019, or until the position is filled. Earlier applications are welcome and an early start date is an advantage.

Please submit your application via the application link below before May 1, 2019.

Further information:
FMT group: fmt.cs.utwente.nl/
Prof.dr. Marielle Stoelinga (m.i.a.stoelinga@utwente.nl)
Project webpage: fmt.cs.utwente.nl/research/projects/FormaSig/

Salary Benefits:

  • A PhD position for four years (38 hrs/week).
  • An excellent outstanding scientific environment: our research group was ranked 1st in the last national research assessment.
  • Full status as an employee at the University of Twente, including pension and health care benefits.
  • Gross salary PhD student: ranging from € 2.325,00 (1st year) to € 2.972,00 (4th year) per month, plus holiday allowance (8%) and end-of-year bonus (8.3%).
  • Extensive opportunities for professional and personal development.
  • Good secondary conditions, in accordance with the collective labour agreement CAO-NU for Dutch universities.
  • A green and lively campus, with excellent sports facilities and many other activities.
Starting date of the position: as soon as possible, to be discussed.

PhD students will be members of the Twente Graduate School in the research program 'Dependable and Secure Computing'. The research program offers advanced courses to deepen your scientific knowledge in preparation to your future career (within or outside academia). We provide our PhD students with excellent opportunities to broaden their personal knowledge and to professionalize their academic skills. Participation in national and/or international summer schools and workshops and visits to other prestigious research institutes and universities can be part of this program.

Work Hours:

38 hours per week

Address:

Drienerlolaan 5